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Datasheet File OCR Text:

M41ST87Y M41ST87W
5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM
Features

5.0, 3.3, or 3.0 V operation 400 kHz I2C bus NVRAM supervisor to non-volatize external LPSRAM 2.5 to 5.5 V oscillator operating voltage Automatic switchover and deselect circuitry Choice of power-fail deselect voltages - M41ST87Y: THS = 1: VPFD 4.63 V; VCC = 4.75 to 5.5 V THS = 0: VPFD 4.37 V; VCC = 4.5 to 5.5 V - M41ST87W: THS = 1: VPFD 2.9 V; VCC = 3.0 to 3.6 V THS = 0: VPFD 2.63 V; VCC = 2.7 to 3.6 V Two independent power-fail comparators (1.25 V reference) Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 128 bytes of clearable, general purpose NVRAM Programmable alarm and interrupt function (valid even during battery backup mode) Programmable watchdog timer Unique electronic serial number (8-byte) 32 kHz frequency output available upon poweron Microprocessor power-on reset output Battery low flag Ultra-low battery supply current of 500 nA (typ) Embedded crystal
28-pin, (300 mil) SOX28 (MX)

Security features

Tamper indication circuits with timestamp and RAM clear LPSRAM clear function (TPCLR) Packaging includes a 28-lead, embedded crystal SOIC Oscillator stop detection
September 2008
Rev 7
1/48
www.st.com 1
Contents
M41ST87Y, M41ST87W
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 2.3 2.4 2.5 2.6
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Tamper detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Tamper register bits (tamper 1 and tamper 2) . . . . . . . . . . . . . . . . . . . . . 17
2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.6.9 Tamper enable bits (TEB1 and TEB2) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Tamper bits (TB1 and TB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Tamper interrupt enable bits (TIE1 and TIE2) . . . . . . . . . . . . . . . . . . . . 18 Tamper connect mode bit (TCM1 and TCM2) . . . . . . . . . . . . . . . . . . . . 18 Tamper polarity mode bits (TPM1 and TPM2) . . . . . . . . . . . . . . . . . . . . 18 Tamper detect sampling (TDS1 and TDS2) . . . . . . . . . . . . . . . . . . . . . . 21 Tamper current high/tamper current low (TCHI/TCLO1 and TCHI/TCLO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RAM clear (CLR1 and CLR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RAM clear external (CLR1EXT and CLR2EXT) . . . . . . . . . . . . . . . . . . . . 21
2.7 2.8 2.9 2.10 2.11
Tamper detection operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal tamper pull-up/down current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Avoiding inadvertent tampers (normally closed configuration) . . . . . . . . . 26 Tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.0.1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M41ST87Y, M41ST87W
Contents
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17
TIMEKEEPER(R) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Full-time 32 kHz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power-fail comparators (1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power-fail outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 trec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Electronic serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/48
List of tables
M41ST87Y, M41ST87W
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Tamper detection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Tamper detection current (normally closed - TCMX = '0') . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Tamper detect timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Calculated cut-off frequency for typical capacitance and resistance values. . . . . . . . . . . . 26 TIMEKEEPER(R) register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 trec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SOX28 - 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data . . . 45 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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M41ST87Y, M41ST87W
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 28-pin, 300 mil SOIC (MX) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WRITE cycle timing: RTC & external SRAM control signals. . . . . . . . . . . . . . . . . . . . . . . . 16 Tamper detect connection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Tamper detect output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Basic tamper detect options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Tamper detect sampling options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Tamper current options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Tamper output timing (with CLR1EXT or CLR2EXT = '1'). . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RAM clear hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Low-pass filter implementation for noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RSTIN1 & RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SOX28 - 28-lead plastic small outline, 300 mils, embedded crystal outline. . . . . . . . . . . . 45
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Description
M41ST87Y, M41ST87W
1
Description
The M41ST87Y/W serial TIMEKEEPER(R)/controller SRAM is a low power 1280-bit, static CMOS SRAM organized as 160 bytes by 8 bits. A built-in 32.768 kHz oscillator (internal crystal-controlled) and 8 bytes of the SRAM (see Table 7 ) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 11 bytes of RAM provide calibration, status/control of alarm, watchdog, tamper, and square wave functions. 8 bytes of ROM and finally 128 bytes of user RAM are also provided. Addresses and data are transferred serially via a two line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41ST87Y/W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, tamper detection, watchdog timer, and programmable square wave output. Other features include a power-on reset as well as two additional debounced inputs (RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30 and 31 day months are made automatically.
1.1
Security features
Two fully independent tamper detection Inputs allow monitoring of multiple locations within the system. Programmable bits provide both, "normally open" and "normally closed" switch monitoring. Time stamping of the tamper event is automatically provided. There is also an option allowing data stored in either internal memory (128 bytes), and/or external memory to be cleared, protecting sensitive information in the event tampering occurs. By embedding the 32 kHz crystal in the package, the clock is completely isolated from external tampering. An oscillator fail bit (OF) is also provided to ensure correct operation of the oscillator. The M41ST87Y/W is supplied in a 28-pin, 300 mil SOIC package (MX) which includes an embedded 32 kHz crystal. The SOIC package is shipped in plastic anti-static tubes or in tape & reel form. The 300 mil, embedded crystal SOIC requires only a user-supplied battery to provide nonvolatile operation.
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M41ST87Y, M41ST87W Figure 1. Logic diagram
VCC VBAT
Description
SCL ECON SDA EX RSTIN1 RSTIN2 WDI PFI1 VOUT PFI2 F32k TP1IN TP2IN (1) M41ST87Y M41ST87W RST(1) IRQ/OUT(1) SQW/FT(2) PFO1(2) PFO2(2)
TPCLR
VSS
1. Open drain output 2. Programmable output (open drain or full-CMOS)
AI07023
Figure 2.
28-pin, 300 mil SOIC (MX) connections
NF NF NF NF NC NC PFO2 SQW/FT WDI RSTIN1 RSTIN2 PFO1 PFI2 VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M41ST87Y 8 M41ST87W 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC EX IRQ/OUT VOUT TP2IN PFI1 SCL F32k TP1IN RST TPCLR SDA ECON VBAT
AI07025b
Note:
No function (NF) and no connect (NC) pins should be tied to VSS. Pins 1, 2, 3, and 4 are internally shorted together.
7/48
Description Table 1.
ECON EX IRQ/OUT PFI1 PFI2 PFO1(2) PFO2(2) RST(1) RSTIN1 RSTIN2 SCL SDA SQW/FT(2) WDI VCC VOUT VSS F32k(1) TP1IN TP2IN TPCLR VBAT NF(3) NC(3)
1. Open drain output 2. Programmable output (open drain or full-CMOS) 3. Should be connected to VSS.
(1)
M41ST87Y, M41ST87W Signal names
Conditioned chip enable output External chip enable Interrupt/out output (open drain) Power fail input 1 Power fail input 2 Power fail output 1 Power fail output 2 Reset output (open drain) Reset 1 input Reset 2 input Serial clock input Serial data input/output Square wave output/frequency test Watchdog input Supply voltage Voltage output Ground 32 kHz square wave output (open drain) Tamper pin 1 input Tamper pin 2 input Tamper pin RAM clear Positive battery pin input No function No connect
8/48
M41ST87Y, M41ST87W Figure 3. Block diagram
Description
REAL TIME CLOCK CALENDAR SDA I2C INTERFACE SCL Crystal VOUT 128 BYTES USER RAM 8 BYTES ROM OFIE RTC w/ALARM & CALIBRATION WATCHDOG SQUARE WAVE CLRX 2 TPXIN WDI VCC VBAT BL TAMPER CLRXEXT AFE WDS IRQ/OUT
(1)
32KHz OSCILLATOR
TIEX
SQW/FT(2) TPCLR VOUT F32k(1)
VSS
VBL
COMPARE
VSO
COMPARE
VPFD RSTIN1 RSTIN2
COMPARE
POR RST
(1)
EX PFI1 1.25V (Internal) PFI2 1.25V (Internal) COMPARE
ECON PFO1(2)
COMPARE
PFO2(2)
AI07026
1. Open drain output. 2. Programmable output (open drain or full-CMOS); if open drain option is selected and if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0 V when VCC = 0 V (during battery backup mode).
9/48
Description Figure 4. Hardware hookup
Inhibit Unregulated Voltage VIN VCC 5V Regulator VCC TP1IN TP2IN Inhibit VIN VCC 3.3V Regulator EX SCL WDI For monitoring of additional voltage sources Pushbutton Reset R3 RSTIN1 RSTIN2 SDA RST SQW/FT PFO1 PFI1 R2 PFI2 VSS R4 VBAT IRQ/OUT F32k PFO2 M41ST87Y/W TPCLR VOUT ECON
M41ST87Y, M41ST87W
VCC E
Low-Power SRAM
To RST To LED Display To NMI
R1
To INT To 32kHz
AI07027
10/48
M41ST87Y, M41ST87W
Operating modes
2
Operating modes
The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 160 bytes contained in the device can then be accessed sequentially in the following order: 00h. 01h. 02h. 03h. 04h. 05h. 06h. 07h. 08h. 09h. Tenths/hundredths of a second register Seconds register Minutes register Century/hours register Day register Date register Month register Year register Control register Watchdog register
0Ah-0Eh. Alarm registers 0Fh. 10h-12h. 13h. 14h. 15h. 16h-1Dh. 1Eh-1Fh. 20h-9Fh. Flag register Reserved Square wave Tamper register 1 Tamper register 2 Serial number (8 bytes) Reserved (2 bytes) User RAM (128 bytes)
The M41ST87Y/W clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). For more information on battery storage life refer to application note AN1012.
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Operating modes
M41ST87Y, M41ST87W
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this
12/48
M41ST87Y, M41ST87W
Operating modes
case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 5. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 6.
Acknowledgement sequence
CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
START SCL FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 7.
Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
13/48
Operating modes Table 2.
Symbol fSCL tBUF tEXPD tF tHD:DAT(2) tHD:STA tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO SCL clock frequency Time the bus must be free before a new transmission can start EX to ECON propagation delay SDA and SCL fall time Data hold time START condition hold time (after this period the first clock pulse is generated) Clock high period Clock low period SDA and SCL rise time Data setup time START condition setup time (only relevant for a repeated start condition) STOP condition setup time M41ST87Y M41ST87W
M41ST87Y, M41ST87W
AC characteristics
Parameter(1) Min 0 1.3 10 15 300 0 600 600 1.3 300 100 600 600 Max 400 Unit kHz s ns ns ns s ns ns s ns ns ns ns
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
2.2
READ mode
In this mode the master reads the M41ST87Y/W slave after setting the slave address (see Figure 8 on page 15). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41ST87Y/W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 9 on page 15). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock or RAM address.
Note:
This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41ST87Y/W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 10 on page 15).
14/48
M41ST87Y, M41ST87W Figure 8. Slave address location
R/W
Operating modes
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 9.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 10. Alternate READ mode sequence
START
NO ACK
BUS ACTIVITY: MASTER SDA LINE
S ACK
R/W
DATA n ACK
DATA n+1 ACK ACK
DATA n+X
P NO ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00895
STOP
ACK
15/48
Operating modes
M41ST87Y, M41ST87W
2.3
WRITE mode
In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus protocol is shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41ST87Y/W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address (see Figure 8 on page 15) and again after it has received the word address and each data byte.
Figure 11. WRITE mode sequence
START R/W STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK
AI00591
BUS ACTIVITY: MASTER
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
Figure 12. WRITE cycle timing: RTC & external SRAM control signals
EX tEXPD tEXPD ECON
AI03663
2.4
Data retention mode
With valid VCC applied, the M41ST87Y/W can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the M41ST87Y/W will automatically deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD (max) and VPFD (min) (see Figure 27 on page 43, Table 18 on page 44). This is accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is within 0.2 volts of the VBAT. ECON will remain at this level as long as VCC remains at an outof-tolerance condition. When VCC falls below the battery backup switchover voltage (VSO),
16/48
ACK
M41ST87Y, M41ST87W
Operating modes
power input is switched from the VCC pin to the battery, and the clock registers and external SRAM are maintained from the attached battery supply. All outputs become high impedance. The VOUT pin is capable of supplying 100A (for M41ST87W) or 150A (for M41ST87Y) of current to the attached memory with less than 0.3 volts drop under this condition. On power up, when VCC returns to a nominal value, write protection continues for trec by inhibiting ECON. The RST signal also remains active during this time (see Figure 27 on page 43). Note: Most low power SRAMs on the market today can be used with the M41ST87Y/W RTC SUPERVISOR. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M41ST87Y/W and SRAMs to be "Don't Care" once VCC falls below VPFD(min). The SRAM should also guarantee data retention down to VCC = 2.0 volts. The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M41ST87Y/W to determine the total current requirements for data retention. The available battery capacity for the battery of your choice can then be divided by this current to determine the amount of data retention available. For a further more detailed review of lifetime calculations, please see Application Note AN1012.
2.5
Tamper detection circuit
The M41ST87Y/W provides two independent input pins, the tamper pin 1 input (TP1IN) and tamper pin 2 input (TP2IN), which can be used to monitor two separate signals which can result in the associated setting of the tamper bits (TB1 and/or TB2, in flag register 0Fh) if the tamper enable bits (TEB1 and/or TEB2) are enabled, for the respective tamper 1 or tamper 2. The TP1IN pin or TP2IN pin may be set to indicate a tamper event has occurred by either 1) closing a switch to ground or VOUT (normally open), or by 2) opening a switch that was previously closed to ground or VOUT (normally closed), depending on the state of the TCMX bits and the TPMX bits in the tamper register (14h and/or 15h).
2.6
2.6.1
Tamper register bits (tamper 1 and tamper 2)
Tamper enable bits (TEB1 and TEB2)
When set to a logic '1,' this bit will enable the tamper detection circuit. This bit must be set to '0' in order to clear the associated tamper bits (TBX, in 0Fh).
Note:
TEBX should be reset whenever the tamper detect condition is modified.
17/48
Operating modes
M41ST87Y, M41ST87W
2.6.2
Tamper bits (TB1 and TB2)
If the TEBX bit is set, and a tamper condition occurs, the TBX bit will be set to '1.' This bit is "Read-only" and is reset only by setting the TEBX bit to '0.' These bits are located in the flags register 0Fh.
2.6.3
Tamper interrupt enable bits (TIE1 and TIE2)
If this bit is set to a logic '1,' the IRQ/OUT pin will be activated when a tamper event occurs. This function is also valid in battery backup if the ABE bit (alarm in battery backup) is also set to '1' (see Figure 14 on page 20).
Note:
In order to avoid an inadvertent activation of the IRQ/OUT pin due to a prior tamper event, the flag register (0Fh) should be read prior to resetting the TEBX bit.
2.6.4
Tamper connect mode bit (TCM1 and TCM2)
This bit indicates whether the position of the external switch selected by the user is in the normally open (TCMX = '1') or normally closed (TCMX = '0') position (see Figure 13 on page 19 and Figure 15 on page 20).
2.6.5
Tamper polarity mode bits (TPM1 and TPM2)
The state of this bit indicates whether the tamper pin input will be taken high (to VOUT if TPMX = '1') or low (to VSS if TPMX = '0') during a tamper event (see Figure 13 on page 19 and Figure 15 on page 20).
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M41ST87Y, M41ST87W Figure 13. Tamper detect connection options
TAMPER LO (TPMX = 0) I. II. TAMPER HI (TPMX = 1)
Operating modes
NORMALLY OPEN (TCMX = 1)
(1) VOUT TPIN TPIN
III. VOUT(2) TPIN NORMALLY CLOSED (TCMX = 0) TCHI/TCLO = 1 1M TCHI/TCLO = 0 10M
IV. VCC (3) 1M VOUT (Int) 10M
TCHI/TCLO = 1
TCHI/TCLO = 0
AI07075
Note:
These options are connected to those in Table 3.
1. If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') during tCLR will not be detected. 2. If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') will trigger automatically. 3. Optional external resistor to VCC allows the user to bypass sampling when power is "on."
Table 3.
Option I II III IV
Tamper detection truth table
Mode Normally open/tamper to GND(1) Normally open/tamper to VOUT
(1)
TCMX 1 1 0 0
TPMX 0 1 0 1
Normally closed/tamper to GND Normally closed/tamper to VOUT
1. No battery current drawn during battery backup.
19/48
Operating modes Figure 14. Tamper detect output options
User Configuration
M41ST87Y, M41ST87W
TIE1 CLR1EXT TP1 TEB1
(other reset sources)
IRQ - Interrupt the processor on tamper TPCLR - Clear external RAM on tamper RESET OUT CLR - Clear 128 bytes internal RAM on tamper Time stamp tamper event (to RTC)
CLR1
TIE2 TP2 TEB2 CLR2
AI07821
CLR2EXT
Figure 15. Basic tamper detect options
Triggering Event VCC (VOUT) TCMX, TPMX = 1,1
TAMPER HI, NORMALLY OPEN TIEX IRQ - Interrupt the processor on tamper
Tamper Event Output
VCC (VOUT) TCMX, TPMX = 0,0
TAMPER LO, NORMALLY CLOSED User Configuration CLRXEXT TPCLR - Clear external RAM on tamper
TCMX, TPMX = 1,0
TAMPER LO, NORMALLY OPEN
CLRX
VCC (VOUT)
TCMX, TPMX
CLR - Clear internal RAM on tamper
TCMX, TPMX = 0,1
TAMPER HI, NORMALLY CLOSED
Time stamp tamper event
AI07818
20/48
M41ST87Y, M41ST87W
Operating modes
2.6.6
Tamper detect sampling (TDS1 and TDS2)
This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input pin(s) to detect a tamper event when the normally closed switch mode is selected. This allows the user to reduce the current drain when the TEBX bit is enabled while the device is in battery backup (see Table 4 on page 22 and Figure 16 on page 22). Sampling is disabled if the TCMX bit is set to logic '1' (Normally Open). In this case the state of the TDSX bit is a "Don't care."
Note:
The crystal oscillator must be "on" for sampling to be enabled.
2.6.7
Tamper current high/tamper current low (TCHI/TCLO1 and TCHI/TCLO2)
This bit selects the strength of the internal pull-up or pull-down used during the sampling of the normally closed condition. The state of the TCHI/TCLOX bit is a "Don't care" for normally open (TCMX = '1') mode (see Figure 17 on page 23).
2.6.8
RAM clear (CLR1 and CLR2)
When either of these bits and the TEBX bit are set to a logic '1,' the internal 128 bytes of user RAM (see Figure 14 on page 20) will be cleared to all zeros in the event of a tamper condition. The 128 bytes of user RAM will be deselected (invalid data will be read) until the corresponding TEBX bit is reset to '0.'
2.6.9
RAM clear external (CLR1EXT and CLR2EXT)
When either of these bits are set to a logic '1' and the TEBX bit is also set to logic '1,' the external SRAM will be cleared and the RST output enabled (see Figure 14 on page 20 and Figure 19 on page 24).
Note:
The reset output resulting from a tamper event will be the same as a reset resulting from a power-down condition, a watchdog time-out, or a manual reset (RSTIN1 or RSTIN2). This is accomplished by forcing TPCLR high, which if used to control the inhibit pin of the DC regulator (see Figure 19 on page 24) will also switch off VOUT, depriving the external SRAM of power to the VCC pin. VOUT will automatically be disconnected from the battery if the tamper occurs during battery back-up (see Figure 18 on page 23). By inhibiting the DC regulator, the user will also prevent other inputs from sourcing current to the external SRAM, allowing it to retain data. The user may optionally connect an inverting charge pump to the VCC pin of the external SRAM (see Figure 19 on page 24). Depending on the process technology used for the manufacturing of the external SRAM, clearing the memory may require varying durations of negative potential on the VCC pin. This device configuration will allow the user to program the time needed for their particular application. Control Bits CLRPW0 and CLRPW1 determine the duration TPCLR will be enabled (see Figure 18 on page 23 and Table 5 on page 24).
Note:
When using the inverting charge pump, the user must also provide isolation in the form of two additional small-signal power MOSFETs. These will isolate the VOUT pin from both the negative voltage generated by the charge pump during a tamper condition, and from being pulled to ground by the output of the charge pump when it is in shut-down mode (SHDN = logic low). The gates of both MOSFETs should be connected to TPCLR as shown in Figure 19 on page 24. One n-channel enhancement MOSFET should be placed between
21/48
Operating modes
M41ST87Y, M41ST87W
the output of the inverting charge pump and the VOUT of the M41ST87. The other MOSFET should be an enhancement mode p-channel, and placed between VOUT of the M41ST87 and VCC of the external SRAM. When TPCLR goes high after a tamper condition occurs, the n-channel MOSFET will turn on and the p-channel will turn off. During normal operating conditions, TPCLR will be low and the p-channel will be on, while the n-channel will be off. Table 4.
TDSX 0 0 1 1
Tamper detection current (normally closed - TCMX = '0')
TCHI/TCLOX 0 1 0 1 Tamper circuit mode Continuous monitoring / 10 M pull-up/-down Continuous monitoring / 1 M pull-up/-down Sampling (1Hz) / 10 M pull-up/-down Sampling (1Hz) / 1 M pull-up/-down Current at 3.0 V (typ)(1)(2) 0.3 3.0 0.3 3.0 Unit A A nA nA
1. When calculating battery lifetime, this current should be added to IBAT current listed in Table 17 on page 42. 2. Per tamper detect input
Figure 16. Tamper detect sampling options
VCC (VOUT)
CONTINUOUS MONITORING TAMPER HI, NORMALLY OPEN
VCC (VOUT)
CONTINUOUS MONITORING SAMPLED MONITORING
TDSX = 0 User Configuration TDSX = 1 TCMX, TPMX
TAMPER LO, NORMALLY CLOSED
CONTINUOUS MONITORING TAMPER LO, NORMALLY OPEN
VCC (VOUT)
CONTINUOUS MONITORING TDSX = 0
TAMPER HI, NORMALLY CLOSED
SAMPLED MONITORING
TDSX = 1
AI07819
22/48
M41ST87Y, M41ST87W Figure 17. Tamper current options
VCC (VOUT)
CONTINUOUS MONITORING TAMPER HI, NORMALLY OPEN
Operating modes
VCC (VOUT)
CONTINUOUS MONITORING SAMPLED MONITORING
TDSX = 0 User Configuration TDSX = 1 TCMX, TPMX
TAMPER LO, NORMALLY CLOSED
TCHI/TCLO = 1 1M
TCHI/TCLO = 0 10M
User Configuration
TPX (TP1, TP2)
CONTINUOUS MONITORING TAMPER LO, NORMALLY OPEN
VCC (VOUT)
User Configuration
1M TCHI/TCLO = 1
10M TCHI/TCLO = 0
CONTINUOUS MONITORING SAMPLED MONITORING
TDSX = 0
TAMPER HI, NORMALLY CLOSED
TDSX = 1
AI07820
Figure 18. Tamper output timing (with CLR1EXT or CLR2EXT = '1')
TPCLR tCLRD tCLR RST VOUT(1) IRQ/OUT(3) High-Z Tamper Event (TB Bit set) High-Z(2) trec
(4)
ECON
AI07083
1. If connected to a negative charge pump device, this pin must be isolated from the charge pump by using both n-channel and p-channel MOSFETs as illustrated in Figure 19 on page 24. 2. If the device is in battery back-up; NOT on VCC (see Section 2.6.9: RAM clear external (CLR1EXT and CLR2EXT) on page 21). 3. If TIEX = '1.' 4. If ABE = '1.'
23/48
Operating modes Table 5.
Symbol tCLRD(1)
M41ST87Y, M41ST87W
Tamper detect timing
Parameter Tamper RAM clear ext delay CLRPW 1 X 0 CLRPW 0 X 0 1 0 1 Min 1.0(2) Typ 1.5 1 4 8 16 Max 2.0 Unit ms s s s s
tCLR
Tamper clear timing
0 1 1
1. With input capacitance = 70 pF and resistance = 50 . 2. If the OF bit is set, tCLRD(min) = 0.5 ms.
Figure 19. RAM clear hardware hookup
Inverting Charge Pump IN Inhibit VIN VCC 5V Regulator VCC TP1IN TP2IN VOUT EX SCL WDI RSTIN1 Pushbutton Reset RSTIN2 ECON SDA RST SQW/FT PFO1 PFI1 PFI2 VSS VBAT IRQ/OUT F32k To INT To 32kHz PFO2 To RST To LED Display To NMI E Low-Power SRAM
(2)
OUT
Negative Output (-1 x VIN)
(1)
SHDN M41ST87Y/W TPCLR
CAP+ CAP-
VCC
AI07804
1. Most inverting charge pumps drive OUT to ground when device shut down is enabled (SHDN = logic low). Therefore, an nchannel enhancement mode MOSFET should be used to isolate the OUT pin from the VOUT of the M41ST87. 2. In order to avoid turning on an on-chip parasitic diode when driving VOUT negative, a p-channel enhancement mode MOSFET should be used to isolate the VOUT pin from the negative voltage generated by the inverting charge pump.
2.7
Tamper detection operation
The tamper pins are triggered based on the state of an external switch. Two switch mode options are available, "normally open" or "normally closed," based on the setting of the
24/48
M41ST87Y, M41ST87W
Operating modes
tamper connect mode bit (TCMX). If the selected switch mode is normally open (TCMX = '1'), the tamper pin will be triggered by being connected to VSS (if the TPMX bit is set to '0') or to VCC (if the TPMX bit is set to '1'), through the closing of the external switch. When the external switch is closed, the tamper bit will be immediately set, allowing the user to determine if the device has been physically tampered with. If the selected switch mode is normally closed (TCMX = '0'), the tamper pin will be triggered by being pulled to VSS or to VOUT (depending on the state of the TPMX bit), through an internal pull-up/pull-down resistor as a result of opening the external switch. When a tamper event occurs, the tamper bits (TB1 and/or TB2) will be immediately set if TEBX = '1.' If the tamper interrupt enable bit (TIEX) is set to a '1,' the IRQ/OUT pin will also be activated. The IRQ/OUT output is cleared by a READ of the flags register (as seen in Figure 23 on page 33), a reset of the TIE bit to '0,' or the RST output is enabled. Note: In order to avoid an inadvertent activation of the IRQ/OUT pin due to a prior tamper event, the flag register (0Fh) should be read prior to resetting the TEBX bit. The tamper bits are "read only" bits and are reset only by writing the tamper enable bit (TEBX) to '0.' The tamper detect function operates both under normal power, and in battery backup. Even if the trigger event occurs during a power-down condition, the bit will be set correctly.
2.8
Sampling
As the switch mode normally closed (TCMX = '0') requires a greater amount of current to maintain constant monitoring, the M41ST87Y/W offers a programmable tamper detect sampling bit (TDSX) to reduce the current drawn on VCC or VBAT (see Figure 16 on page 22). When enabled, the sampling frequency is once per second (1Hz), for approximately 1 ms. When TEBX is disabled, no current will be drawn by the tamper detection circuit. After a tamper event has been detected, no additional current will be drawn.
Note: Note:
The oscillator must be running for tamper detection to operate in the sampling mode. If the oscillator is stopped, the tamper detection circuit will revert to constant monitoring. Sampling in the tamper high mode (TPMX = '1') may be bypassed while on VCC by connecting the TPXIN pin to VCC through an external resistor. This will allow constant monitoring when VCC is "on" and revert to sampling when in battery backup (see Figure 13 on page 19).
2.9
Internal tamper pull-up/down current
Depending on the capacitive and resistive loading of the tamper pin input (TPXIN), the user may require more or less current from the internal pull-up/down used when monitoring the normally closed switch mode. The state of the tamper current hi/tamper current low bit (TCHI/TCLOX) determines the sizing of the internal pull-up/-down. TCHI/TCLOX = '1' uses a 1 M pull-up/-down resistor, while TCHI/TCLOX = '0' uses a 10 M pull-up/-down resistor (see Figure 17 on page 23).
25/48
Operating modes
M41ST87Y, M41ST87W
2.10
Avoiding inadvertent tampers (normally closed configuration)
In some applications it may be necessary to use a low pass filter to reduce electrical noise on the tamper input pin when the TCMX bit = 0 (normally closed). This is especially true if the tamper detect switch is located some distance (> 6") from the tamper input pin. A low pass filter can prevent unwanted, higher frequency noise from inadvertently being detected as a tamper condition caused by the "antenna-effect" (produced by a longer signal wire or mesh). This low pass filter can be constructed using a series resistor (R) in conjunction with a capacitor (C) on the tamper input pin. The cut-off frequency fc is determined according to the formula:
f c = 1 ( 2 Pi R C )
Figure 20. Low-pass filter implementation for noise immunity
To Tamper Detect Switch R C TPIN
AI11185
Table 6.
Calculated cut-off frequency for typical capacitance and resistance values
R () 1000 1000 5000 5000 10000 10000 C (F) 1.00E-09 1.00E-06 1.00E-09 1.00E-06 1.00E-09 1.00E-06 fc 15.9 MHz 159.2 Hz 31.8 kHz 31.8 Hz 15.9 kHz 15.9 Hz 1/fc (s) 6.28 s 6.28 ms 31.4 s 31.4 ms 62.8 s 62.8 ms
26/48
M41ST87Y, M41ST87W
Operating modes
2.11
Tamper event time-stamp
Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but the event will also be automatically time-stamped. This is accomplished by freezing the normal update of the clock registers (00h through 07h) immediately following a tamper event. Thus, when tampering occurs, the user may first read the time registers to determine exactly when the tamper event occurred, then re-enable the clock update to the current time (and reset the tamper bit, TBX) by resetting the tamper enable bit (TEBX). The time update will then resume and the clock can be read to determine the current time. Both tamper enable bits (TEBX) must always be set to '0' in order to read the current time. In the event of multiple tampers, the time-stamp will reflect the initial tamper event.
Note:
If the TEBX bit is set, the tamper event time-stamp will take precedence over the power down time-stamp (see Section 3.0.1: Power-down time-stamp on page 28) and the HT bit (halt update) will not be set during the power-down event. If both are needed, the power down time-stamp may be accomplished by writing the time into the general purpose RAM memory space when PFO is asserted.
27/48
Clock operation
M41ST87Y, M41ST87W
3
Clock operation
The eight byte clock register (see Table 7 on page 29) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers.
Note:
A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to "00," and tenths/hundredths of seconds cannot be written to any value other than "00." Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the control register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second (typical).
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the OFIE bit, CLRPW0 bit, CLRPW1 bit, THS bit, and so forth, will result in an update of the system clock and a reset of the divider chain. This could result in a significant corruption of the current time, especially if the HT bit (see Section 3.0.1: Power-down timestamp) has not been previously reset. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight clock registers may be read one byte at a time, or in a sequential block. The control register (address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.0.1
Power-down time-stamp
Upon power-up following a power failure, the halt update bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER(R) registers, and will allow the user to read the time of the power-down event.
Note:
When the HT bit is set or a tamper event occurs, the tenths/hundredths of a second register (00h) will automatically be reset to a value of "00." All other date and time registers (01h 07h) will retain the value last updated prior to the power-down or tamper event. The internal clock remains accurate and no time is lost as a result of the zeroing of the tenth/hundredths of a second register. When updates are resumed (due to resetting the HT bit or TEB bit), the correct time will be displayed. Resetting the HT bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time.
Note:
If the TEB bit is set, the power down time-stamp will be disabled, and the tamper event timestamp will take precedence (see Section 2.7: Tamper detection operation on page 24).
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M41ST87Y, M41ST87W
Clock operation
3.1
TIMEKEEPER(R) registers
The M41ST87Y/W offers 22 internal registers which contain clock, control, alarm, watchdog, flag, square wave, and tamper data. The clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to a non-clock or RAM address. TIMEKEEPER and alarm registers store data in BCD format. Control, watchdog and square wave registers store data in binary format.
Table 7.
Addr
TIMEKEEPER(R) register map
Data D7 D6 D5 D4 D3 D2 D1 D0 Function/range BCD format 10s/100s seconds Seconds Minutes Century/ Hours Day Date Month Year Control Watchdog Al month Al date Al hour Al min Al sec Flags Reserved Reserved Reserved SQW Tamper1 Tamper2 Serial number 128 user bytes 8-byte 2-byte 00-99 00-59 00-59 0-1/ 00-23 01-7 01-31 01-12 00-99
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h-1Dh 1Eh-1Fh 20h-9Fh ST OFIE CB1 TR PFOD 0 OUT WDS AFE RPT4 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 TEB1 TEB2
0.1 seconds 10 seconds 10 minutes CB0 THS 0 0 10 hours
0.01 seconds Seconds Minutes Hours (24-hour format)
CLRPW1 CLRPW0 32kE Day of week 10 date Date: day of month 0 10M Month 10 Years Year FT S Calibration BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 SQWE ABE Al 10M Alarm month RPT5 AI 10 date Alarm date HT AI 10 hour Alarm hour Alarm 10 minutes Alarm minutes Alarm 10 seconds Alarm seconds AF 0 BL 0 OF TB1 TB2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS2 RS1 RS0 SQWOD 0 0 0 TCHI/ TIE1 TCM1 TPM1 TDS1 CLR1EXT CLR1 TCLO1 TCHI/ TIE2 TCM2 TPM2 TDS2 CLR2EXT CLR2 TCLO2 ROM Reserved
01-12 01-31 00-23 00-59 00-59
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Clock operation
M41ST87Y, M41ST87W
Keys: 0 = Must be set to zero 32kE = 32 kHz output enable bit RB0-RB1 = Watchdog resolution bits RPT1-RPT5 = Alarm repeat mode bits
ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency AF = Alarm flag (read only) AFE = Alarm flag enable bit BL = Battery low flag (read only) BMB0-BMB4 = Watchdog multiplier bits CB0-CB1 = Century bits CLR (1 and 2) = RAM clear bits CLR (1 and 2)EXT = RAM clear external bits CLRPW0 = RAM clear pulse width 0 bit CLRPW1 = RAM clear pulse width 1 bit FT = Frequency test bit HT = Halt update bit OF = Oscillator fail bit OFIE = Oscillator fail interrupt enable bit OUT = Output level PFOD = Power-fail output open drain bit S = Sign bit SQWE = Square wave enable SQWOD = Square wave open drain bit ST = Stop bit TB (1 and 2) = Tamper bits (read only) TCHI/TCLO (1 and 2) = Tamper current hi/tamper current low bits TCM (1 and 2) = Tamper connect mode bits TDS (1 and 2) = Tamper detect sampling bits TEB (1 and 2) = Tamper enable bits THS = Threshold bit TIE (1 and 2) = Tamper interrupt enable bits TPM (1 and 2) = Tamper polarity mode bits TR = trec bit WDS = Watchdog steering bit WDF = Watchdog flag (read only)
3.2
Calibrating the clock
The M41ST87Y/W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed 35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 21 on page 31). Therefore, the M41ST87Y/W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 22: Calibration waveform on page 32. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of
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M41ST87Y, M41ST87W
Clock operation
adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST87Y/W may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, "TIMEKEEPER(R) calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the SQW/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST) is '0,' the frequency test bit (FT) is '1,' and SQWE is '0.' Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. If the SQWOD Bit = '1,' the SQW/FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. Figure 21. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F K = -0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Temperature C
AI07888
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Clock operation Figure 22. Calibration waveform
M41ST87Y, M41ST87W
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.3
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41ST87Y/W is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 8 on page 33 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the alarm condition activates the IRQ/OUT pin as shown in Figure 24 on page 33. To disable alarm, write '0' to the alarm date register and to RPT5-RPT1. If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "alarm seconds," the address pointer will increment to the flag address, causing this situation to occur. The IRQ/OUT output is cleared by a READ to the flags register. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' The IRQ/OUT pin can also be activated in the battery backup mode. The IRQ/OUT will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the flag register at system boot-up to determine if an alarm was generated while the M41ST87Y/W was in the deselect mode during power-up. Figure 24 on page 33 illustrates the backup mode alarm timing.
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M41ST87Y, M41ST87W Figure 23. Alarm interrupt reset waveform
Clock operation
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/OUT
HIGH-Z
AI07086
Table 8.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
Figure 24. Backup mode alarm waveform
VCC VPFD
VSO trec ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/OUT HIGH-Z HIGH-Z
AI07087
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Clock operation
M41ST87Y, M41ST87W
3.4
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The amount of time-out is then determined to be the multiplication of the fivebit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3 seconds).
Note:
The accuracy of the timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M41ST87Y/W sets the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will activate the IRQ/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for trec. The watchdog register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a WRITE of the watchdog register. The time-out period then starts over.
Note:
The WDI pin should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, either a transition of the WDI pin, or a value of 00h needs to be written to the watchdog register in order to clear the IRQ/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared.
3.5
Square wave output
The M41ST87Y/W offers the user a programmable square wave function which is output on the SQW/FT pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 9. Once the selection of the SQW frequency has been completed, the SQW/FT pin can be turned on and off under software control with the square wave enable bit (SQWE) located in Register 0Ah. The SQW/FT output is programmable as an N-channel, open drain output driver, or a fullCMOS output driver. By setting the square wave open drain bit (SQWOD) to a '1,' the output will be configured as an open drain (with IOL as specified in Table 17 on page 42). When SQWOD is set to '0,' the output will be configured as full-CMOS (sink and source current as specified in Table 17 on page 42).
Note:
When configured as open drain (SQWOD = '1'), the SQW/FT pin requires an external pullup resistor.
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M41ST87Y, M41ST87W Table 9. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Clock operation
Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units - kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
3.6
Full-time 32 kHz square wave output
The M41ST87Y/W offers the user a special 32kHz square wave function which defaults to output on the F32k pin (pin 21) as long as VCC VSO, and the oscillator is running (ST bit = '0'). This function is available within one second (typ) of initial power-up and can only be disabled by setting the 32 kE bit to '0' or the ST bit to '1.' If not used, the F32k pin should be disconnected and allowed to float.
Note:
The F32k pin is an open drain which requires an external pull-up resistor.
3.7
Power-on reset
The M41ST87Y/W continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes VPFD(max). The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time.
Note:
A power-on reset will result in resetting the following control bits to '0': OFIE, AFE, ABE, SQWE, FT, WDS, BMB0-BMB4, RB0, RB1, TIE1, and TIE2 (see Table 13 on page 39).
3.8
Reset inputs (RSTIN1 & RSTIN2)
The M41ST87Y/W provides two independent inputs which can generate an output reset. The function of these resets is identical to a reset generated by a power cycle. Table 10 and Figure 25 illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and
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Clock operation
M41ST87Y, M41ST87W
tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100 k resistor. Figure 25. RSTIN1 & RSTIN2 timing waveforms
RSTIN1 tR1 RSTIN2 tR2 Hi-Z RST trec trec
AI07072
Hi-Z
Table 10.
Symbol tR1 tR2
(2) (2)
Reset AC characteristics
Parameter(1) RSTIN1 low to RST low (min pulse width) RSTIN2 low to RSTIN2 high (min pulse width) RSTIN1 or RSTIN2 high to RST high Min 100 100 96 Max 200 200 98(3) Unit ns ns ms
trec(3)
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted). 2. Pulse widths of less than 100 ns will result in no RESET (for noise immunity). 3. Programmable (see Table 12 on page 39). Same function as power-on reset.
3.9
Power-fail comparators (1 and 2)
Two power-fail inputs (PFI1 and PFI2) are compared to an internal reference voltage (1.25V). If either PFI1 or PFI2 is less than the power-fail threshold (VPFI), the associated power-fail output (PFO1 or PFO2) will go low. This function is intended for use as an under-voltage detector to signal a failing power supply. Typically PFI1 and PFI2 are connected through external voltage dividers (see Figure 4 on page 10) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI1 or PFI2 falls below VPFI several milliseconds before the regulated VCC input to the M41ST87Y/W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO1 and PFO2 go (or remain) low. This occurs after VCC drops below VPFD(min). When power returns, PFO1 and PFO2 are forced high, irrespective of VPFI for the write protect time (trec), which is the time from VPFD(max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO1 and PFO2 follow PFI1 and PFI2. If the comparator is unused, PFI1 or PFI2 should be connected to VSS and the associated PFO1 or PFO2 left unconnected.
3.10
Power-fail outputs
The PFO1 and PFO2 outputs are programmable as N-channel, open drain output drivers, or full-CMOS output drivers. By setting the power-fail output open drain bit (PFOD) to a '1,' the
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M41ST87Y, M41ST87W
Clock operation
output will be configured as open drain (with IOL as specified in Table 17 on page 42). When PFOD is set to '0,' the outputs will be configured as full-CMOS (sink and source current as specified in Table 17 on page 42). Note: When configured as open drain (PFOD = '1'), PFO1 and PFO2 will require an external pullup resistor.
3.11
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle leap years correctly. See Table 11 on page 38 for additional explanation.
3.12
Output driver pin
When the TIE bit, OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D7 (OUT Bit) is a '0,' then the IRQ/OUT pin will be driven low. With the ABE bit set to '1,' the OUT pin will continue to be driven low in battery backup.
Note:
The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.13
Battery low warning
The M41ST87Y/W automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The battery may be replaced while VCC is applied to the device. The M41ST87Y/W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
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Clock operation
M41ST87Y, M41ST87W
3.14
trec bit
Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic continuation of the deselect time after VCC reaches VPFD. This allows for a voltage settling time before WRITEs may again be performed to the device after a power-down condition. The trec bit will allow the user to set the length of this deselect time as defined by Table 12 on page 39.
3.15
Electronic serial number
The M41ST87Y/W has a unique 8-byte lasered, serial number with parity. This serial number is "read only" and is generated such that no two devices will contain an identical number.
3.16
Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. The following conditions can cause the OF bit to be set:

The first time power is applied (defaults to a '1' on power-up). The voltage present on VCC or battery is insufficient to support oscillation. The ST bit is set to '1.'
If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ/OUT pin will also be activated. The IRQ/OUT output is cleared by resetting the OF bit to '0,' resetting the OFIE bit to '0,' or the RST output is enabled (NOT by reading the flag register). The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to '0.' This function operates both under normal power and in battery backup. If the trigger event occurs during a powerdown condition, this bit will be set correctly. Note: The ABE bit must be set to '1' for the IRQ/OUT pin to be activated in battery backup.
3.17
Initial power-on defaults
See Table 13 on page 39.
Table 11.
Century bits examples
CB1 0 1 0 1 Leap year? Yes No No No Example(1) 2000 2100 2200 2300
CB0 0 0 1 1
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
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M41ST87Y, M41ST87W Table 12. trec definitions
STOP bit (ST) Min 0 1 X 96 40 50 trec time Max 98(1) 200 2000
Clock operation
trec bit (TR) 0 0 1
1. Default setting
Units ms ms s
Table 13.
Default values
TR 0 UC ST 0 UC OF 1 UC OFIE 0 0 HT(1) 1 1 Out 1 UC FT 0 0 AFE 0 0
Condition Initial power-up Subsequent power-up (with battery backup)(2)(3)
Condition Initial power-up Subsequent power-up (with battery backup)(2)(3)
ABE 0 0
SQWE 0 0
SQWOD 1 UC
PFOD 1 UC
Watchdog register(4) 0 0
Condition Initial power-up Subsequent power-up (with battery backup)(2)
32kE 1(5) UC
THS 0 UC
TEB1 and 2 0 UC
TCM1 and 2 0 UC
TPM1 and 2 0 UC
TDS1 and 2 0 UC
Condition Initial power-up Subsequent power-up (with battery backup)(2)
TCHI/TCLO1 and 2 0 UC
CLR1 and 2 0 UC
TIE1 and 2 0 0
CLRPW0 0 UC
CLRPW1 0 UC
CLR1EXT and CLR2EXT 0 UC
1. When TEBX is set to '1,' the HT bit will not be set on power-down (tamper time-stamp will have precedence). 2. UC = unchanged. 3. = VCC rising; = VCC falling. 4. WDS, BMB0-BMB4, RB0, RB1. 5. 32 kHz output valid only on VCC.
Note:
All other control bits are undetermined.
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Maximum ratings
M41ST87Y, M41ST87W
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 14.
Symbol TSTG TSLD
(1)
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation M41ST87Y M41ST87W Value -55 to 125 240 -0.3 to VCC+0.3 -0.3 to 7.0 -0.3 to 4.6 20 1 Unit C C V V V mA W
VIO VCC IO PD
1. Reflow at peak temperature of 240C (total thermal budget not to exceed 180C between 90 to 150 seconds).
Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode.
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M41ST87Y, M41ST87W
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 15. DC and AC measurement conditions
Parameter VCC supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M41ST87Y 4.5 to 5.5 V -40 to 85C 100 pF 50 ns 0.2 to 0.8VCC 0.3 to 0.7VCC M41ST87W 2.7 to 3.6 V -40 to 85C 50 pF 50 ns 0.2 to 0.8VCC 0.3 to 0.7VCC
Note:
Output high Z is defined as the point where data is no longer driven. Figure 26. AC testing input/output waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Note:
50 pF for M41ST87W. Table 16.
Symbol CIN COUT(3) tLP Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL)
Capacitance
Parameter(1)(2) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25C, f = 1 MHz. 3. Outputs are deselected.
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DC and AC parameters Table 17.
Sym
M41ST87Y, M41ST87W
DC characteristics
Parameter Test condition(1) M41ST87Y Min Typ Max 700 Min M41ST87W Typ 500 50 1.4 1 1 25 1 175 100 VCC + 0.3 0.7VCC 0.3VCC 3.5(6) -0.3 2.5 2.4 5.5 2.9 0.4 0.4 4.50 4.75 1.275 70 1.275 70 1.225 2.55 2.80 1.225 2.62 2.88 1.250 20 1.250 20 2.5 500 500 0.4 0.4 2.70 3.00 1.275 70 1.275 70 3.6 3.0 -25 2 0.75 0.50 1 25 1 100 100 VCC + 0.3 0.3VCC 3.5(6) Max 700 Unit nA nA mA mA A nA A mA A V V V V V V V V V V V mV V mV V W
Battery current 500 TA = 25C, VCC = 0 V, OSC ON IBAT(2) Battery current VBAT = 3 V 50 OSC OFF ICC1 Supply current f = 400 kHz Supply current ICC2 SCL, SDA = VCC - 0.3 V (standby) Input leakage 0V VIN VCC current ILI(3) Input leakage -25 2 current (PFI) Output leakage 0V VIN VCC ILO(4) current V current IOUT1(5) OUT VOUT1 > VCC - 0.3 V (active) VOUT current VOUT2 > VBAT - 0.3 V IOUT2 (battery backup) Input high VIH 0.7VCC voltage VIL Input low voltage -0.3 2.5 3.0 VBAT Battery voltage Output high VOH(7) 2.4 IOH = -1.0 mA voltage Pull-up supply voltage IRQ/OUT, RST, F32k (open drain) V (battery 2.9 VOHB(8) OH IOUT2 = -1.0 A(9) backup) Output low IOL = 3.0 mA voltage Output low VOL voltage IOL = 10 mA (open drain)(10) THS bit = 0 4.20 4.35 Power fail VPFD deselect THS bit = 1 4.50 4.60 VCC = 5 V(Y) PFI input 1.225 1.250 VPFI1 threshold VCC = 3 V(W) PFI hysteresis PFI rising 20 VCC = 5 V(Y) PFI input 1.225 1.250 VPFI2 threshold VCC = 3 V(W) PFI hysteresis PFI rising 20 Battery backup VSO 2.5 switchover Switch RSW resistance on tamper pin
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted). 2. Measured with VOUT and ECON open. Not including tamper detection current (see Table 4 on page 22). 3. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 K resistor. WDI internally pulled-down to VSS through 100 K resistor.
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M41ST87Y, M41ST87W
DC and AC parameters
4. Outputs deselected. 5. External SRAM must match RTC supervisor chip VCC specification. 6. For rechargeable backup, VBAT (max) may be considered VCC. 7. For PFO1 and PFO2 (if PFOD = '0'), SQW/FT (if SQWOD = '0'), and TPCLR pins (CMOS). 8. Conditioned output (ECON) can only sustain CMOS leakage current in the battery backup mode. Higher leakage currents will reduce battery life. 9. TPCLR output can source -300 A (typ) for VBAT = 2.9 V. 10. For IRQ/OUT, SQW/FT (if SQWOD = '1'), PFO1 and PFO2 (if PFOD = '1'), RST, SDA, and F32k pins (open drain).
Figure 27. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD PFO tRB trec tR
VALID
VALID
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
ECON
AI07085
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DC and AC parameters Table 18.
Symbol tF(2) tFB
(3)
M41ST87Y, M41ST87W
Power down/up AC characteristics
Parameter(1) VPFD(max) to VPFD(min) VCC fall time VPFD(min) to VSS VCC fall time EX at VIH before power down PFI to PFO propagation delay VPFD(min) to VPFD(max) VCC rise time VSS to VPFD(min) VCC rise time Power-up deselect time 10 1 96 98
(4)
Min 300 10 0
Typ
Max
Unit s s s
tPD tPFD tR tRB trec
15
25
s s s ms
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted). 2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD(min). 3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. Programmable (see Table 12 on page 39)
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M41ST87Y, M41ST87W
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 28. SOX28 - 28-lead plastic small outline, 300 mils, embedded crystal outline
D
14 1
h x 45
C E H
15
28
A2 B SO-E e A1
A ddd A1 L
Note: Table 19.
Symbol
Drawing is not to scale. SOX28 - 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data
millimeters Typ A A1 A2 B C D ddd E e H L a N 1.27 7.57 - 10.16 0.51 0 28 Min 2.44 0.15 2.29 0.41 0.20 17.91 Max 2.69 0.31 2.39 0.51 0.31 18.01 0.10 7.67 - 10.52 0.81 8 0.050 0.298 - 0.400 0.020 0 28 Typ inches Min 0.096 0.006 0.090 0.016 0.008 0.705 Max 0.106 0.012 0.094 0.020 0.012 0.709 0.004 0.302 - 0.414 0.032 8
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Part numbering
M41ST87Y, M41ST87W
7
Part numbering
Table 20.
Example:
Ordering information scheme
M41ST 87Y MX 6
Device type M41ST
Supply voltage and write protect voltage 87Y = VCC = 4.75 to 5.5 V THS bit = '1': 4.50 V VPFD 4.75 V VCC = 4.5 to 5.5 V THS bit = '0': 4.20 V VPFD 4.50 V 87W = VCC = 3.0 to 3.6 V; THS bit = '1': 2.80 V VPFD 3.00 V VCC = 2.7 to 3.6 V; THS bit = '0': 2.55 V VPFD 2.70 V
Package MX(1)(2)= SOX28
Temperature range 6 = -40 to 85C
Shipping method blank = ECOPACK(R) package, tubes TR = ECOPACK(R) package, tape & reel
1. The SOX28 package includes an embedded 32,768 Hz crystal. 2. Lead-free second level interconnect and RoHS compliant (by exemption).
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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M41ST87Y, M41ST87W
Revision history
8
Revision history
Table 21.
Date May-2002 23-Apr-2003 10-Jul-2003 11-Sep-2003 15-Jun-2004 7-Sep-2004 29-Jun-2005 28-Mar-2006 10-Sep-2008
Document revision history
Revision 1 2 2.1 2.2 3 4 5 6 7 First issue. Document promoted to Preliminary Data. Update tamper information ( Figure 3, 4, 13, 14, 15; Table 17, 4, 12). Update electrical, charge pump, and clock information (Table 17; Figure 4, 18, 19). Reformatted; added Lead-free information; updated characteristics (Figure 2; Table 1, 14, 17, 20). Update maximum ratings (Table 14). Clarify NC connections, add Inadvertent Tamper, update MX attribute (Figure 2, 20; Table 1, 6, 20). Update to "Avoiding Inadvertent Tamper paragraph" paragraph. Reformatted document and title change; updated cover page, Figure 3, 14, 19, Section 6: Package mechanical data. Changes
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M41ST87Y, M41ST87W
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